why in lower metal layers the resistance /capacitance increases.

 

In lower metal layers the cross sectional area of the metal decreases. As the cross sectional area decreases the resistance increases.  So the resistance is more in lower metal layers. 

Hence to reduce the delay its suggested to move to higher metal layers. 

Also lower metal layers are more prone to coupling cap as the distance between the two metal layers is less. If you want to avoid more cap move to higher layers or increase the distance between the two metals routed side by side. 

From the formula below if the distance between two metals decreases the capacitance increases. 

A is area of contact of two metals. 

D is the distance. 

E0 is the permitivity of free space in general here it is permitivity of the dielectric / the permitiivity of the material between the two metal layers. 

why cant we define two logically exclusive clocks as physically exclusive

 What are logically exclusive clocks

             They are clocks which are not active at the same time. They might be two clocks which are muxed a the mux with a select pin. 

set_clock_groups -logically_exclusive CLK1 CLK2

  

Take the example below there are two clocks CLK1 and CLK2. 

Here the two clocks at the mux output would be exclusive to each other. 

But you see at the input A first the CLK1 is propagating to few sinks 

There might be crosstalk physically between the CLK1 clock arm going to the input registers and that of the mux output clocks CLK1/ CLK2. 

Here if we defined two clocks as logically asynchronous then the crosstalk would be calculated between the CLK1 and CLK2

Here if we could have defined the two clocks as physically exclusive there would be no crosstalk calculated. 

physically exclusive 

               These are clocks which do not exist at the same time on the chip. They might be a scan shift clock and a func clock.  These two clcoks do not exist at the same time on the chip.