If there is setup violation, the frequency of chip can be reduced
and we can make the chip still function. But if there is hold violation then
your chip is lost for ever. This is the most used phrase in physical design.
But did you ever try to analyse why the hold violations does not depend on the
frequency of the chip ?
First of all let us understand Setup and hold checks completely
Imagine data is travelling from FF1 to FF2 as shown in the figure.
Look at the timing diagram below
- Data1(clock cycle1 data of FF1 ) is being sampled at FF2 in clock cycle2
- Data2 (clock cycle2 data of FF1) is on its way to FF2 already
From the figure
Setup check
It says
that the data sampled from FF1 at cycle 1 should reach FF2 in cycle 2 before
FF2 setup time.
Equation
Tc2q (FF1) + Tcomb = Tclk -Tsetup
Hold check
It says that the current data ==>Data 2, which
is sampled from FF1 at cycle2, should
not arrive at FF2 at cycle2 before FF2 hold time. ( because it messes up with Data1 which is being currently captured
by FF2 in cycle2 )
In other words there Data2 from FF1 should not mess with Data1 which is already at FF2 which is currently being sampled
T.c2q (clock to Q delay of FF1) +Tcomb >= T (hold )
Your clock->Q delay and Tcomb are not at all dependent on the clock period. Hence your hold is independent of clock frequency.
